MCQMediumJEE 2025Logic Gates

JEE Physics 2025 Question with Solution

The Boolean expression Y=ABC+AC\mathrm{Y}=\mathrm{A} \overline{\mathrm{B}} \mathrm{C}+\overline{\mathrm{AC}} can be realised with which of the following gate configurations.

A. One 33-input AND gate, 33 NOT gates and one 22-input OR gate, One 22-input AND gate

B. One 33-input AND gate, 11 NOT gate, One 22-input NOR gate and one 22-input OR gate

C. 33-input OR gate, 33 NOT gates and one 22-input AND gate

Choose the correct answer from the options given below:

  • A

    B, C Only

  • B

    A,B Only

  • C

    A, B, C Only

  • D

    A, C Only

Answer

Correct answer:B

Step-by-step solution

Standard Method

Given: Boolean expression

Y=ABC+ACY = A\overline{B}C + \overline{AC}

Find: Which gate configurations can realise the expression.

Two digital logic circuit configurations labeled A and B, showing inputs A, B, C connected through NOT, AND, NOR, and OR gates to produce output Y.

From the extracted solution, configuration A and configuration B are identified as matching the Boolean expression.

The solution explicitly states:

  • A. One 33-input AND gate, 33 NOT gates and one 22-input OR gate, One 22-input AND gate
  • B. One 33-input AND gate, 11 NOT gate, One 22-input NOR gate and one 22-input OR gate

Therefore, the correct combination is A, B Only.

The correct option is B.

Common mistakes

  • Mistake: Treating AC\overline{AC} as AC\overline{A}\,\overline{C} without checking the gate implementation carefully. Why wrong: the complemented product is naturally realised by a NOR/NAND-style combination depending on the circuit structure. What to do instead: identify whether the complement applies to the whole product term or to individual variables before mapping gates.

  • Mistake: Ignoring that the options refer to configurations A, B, and C shown in the question, not to answer labels A, B, C, D. Why wrong: this mixes circuit names with multiple-choice option labels. What to do instead: first determine which circuit configurations are correct, then select the matching final option.

  • Mistake: Assuming configuration C must also work without verifying each gate sequence. Why wrong: logic circuit realisation depends on exact inversion and combination of signals. What to do instead: trace the signal path term by term and compare it with ABC+ACA\overline{B}C + \overline{AC}.

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