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MCQMediumJEE Main 2026 · 22 January, Shift 2Logic Gates

Physics Question from JEE Main 2026 · 22 January, Shift 2

The correct truth table for the given input data of the following logic gate is:

Logic circuit with inputs A and B entering an AND gate followed by a NOT gate, inputs C and D entering an OR gate, both outputs feeding an AND gate followed by a NOT gate to produce Y output.
  • A

    ABCDY11011001101010011111\begin{array}{|c|c|c|c|c|}\hline A & B & C & D & Y \\ \hline 1 & 1 & 0 & 1 & 1 \\ 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 0 & 0 \\ 1 & 1 & 1 & 1 & 1 \\ \hline \end{array}

  • B

    ABCDY11011001101010111110\begin{array}{|c|c|c|c|c|}\hline A & B & C & D & Y \\ \hline 1 & 1 & 0 & 1 & 1 \\ 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 \\ 1 & 1 & 1 & 1 & 0 \\ \hline \end{array}

  • C

    ABCDY11010001101010111111\begin{array}{|c|c|c|c|c|}\hline A & B & C & D & Y \\ \hline 1 & 1 & 0 & 1 & 0 \\ 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 \\ 1 & 1 & 1 & 1 & 1 \\ \hline \end{array}

  • D

    ABCDY11010001111010111111\begin{array}{|c|c|c|c|c|}\hline A & B & C & D & Y \\ \hline 1 & 1 & 0 & 1 & 0 \\ 0 & 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 0 & 1 \\ 1 & 1 & 1 & 1 & 1 \\ \hline \end{array}

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