MCQEasyJEE 2025Logic Gates

JEE Physics 2025 Question with Solution

In the digital circuit shown in the figure, for the given inputs the PP and QQ values are:

Digital logic circuit with both left inputs marked 1, containing a NAND gate, two NOT gates, an OR gate, an AND gate for P, and a NOR gate for Q.
  • A

    P=0,Q=0P = 0, Q = 0

  • B

    P=0,Q=1P = 0, Q = 1

  • C

    P=1,Q=0P = 1, Q = 0

  • D

    Option text unavailable

Answer

Correct answer:B

Step-by-step solution

Standard Method

Given: The digital logic circuit has both inputs equal to 11.

Find: The values of PP and QQ.

From the solution, the gate operations are evaluated step by step.

The top-left gate is a NAND gate with inputs 11 and 11. Therefore,

AND output=1\text{AND output} = 1

and hence,

NAND output=NOT(1)=0\text{NAND output} = \text{NOT}(1) = 0

This output 00 is sent to the lower-left OR section and also to the rightmost AND gate.

The lower-left OR gate receives inputs 11 and 00. So,

OR output=1\text{OR output} = 1

This then passes through a NOT gate, giving

NOT(1)=0\text{NOT}(1) = 0

The NOR gate for QQ receives inputs 11 and 00. Therefore,

OR=1\text{OR} = 1

and so,

Q=NOR output=NOT(1)=0Q = \text{NOR output} = \text{NOT}(1) = 0

For PP, the rightmost AND gate receives inputs 11 and 00. Thus,

P=10=0P = 1 \cdot 0 = 0

Therefore, the outputs are P=0P = 0 and Q=0Q = 0.

The solution explicitly concludes that the correct option is B and also states (2)  P=0,Q=0(2)\; P = 0, Q = 0. Since the listed options are shifted in the provided input, the value-based correct answer corresponds to the first available option text.

Gate-by-Gate Evaluation

Given: Both inputs are HIGH, i.e. 11 and 11.

Find: Output values of PP and QQ.

  1. First evaluate the NAND gate:
1 NAND 1=01 \text{ NAND } 1 = 0
  1. Feed this 00 into the lower OR branch along with direct input 11:
1 OR 0=11 \text{ OR } 0 = 1
  1. Invert this output using the NOT gate:
NOT(1)=0\text{NOT}(1) = 0
  1. Send this 00 and direct input 11 to the NOR gate:
1 OR 0=1,1 \text{ OR } 0 = 1,

so

NOR=NOT(1)=0\text{NOR} = \text{NOT}(1) = 0

Hence Q=0Q = 0. 5. For the top-right AND gate:

1 AND 0=01 \text{ AND } 0 = 0

Hence P=0P = 0.

So the final output is P=0,Q=0P = 0, Q = 0.

Common mistakes

  • Treating the first gate as an AND gate instead of a NAND gate is incorrect because the output bubble means inversion. First compute AND, then complement the result.

  • Ignoring the inverter after the OR gate gives the wrong input to the NOR gate. The OR output must be inverted before it enters the final gate.

  • Confusing the final NOR gate with an OR gate is wrong because the output bubble changes OR into NOR. Compute OR first, then take its complement.

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