For the circuit shown above, the equivalent gate is: — Solution | JEE Physics

MCQMediumJEE 2025Logic Gates

Logic circuit with inputs A and B feeding a NAND gate on the top branch and a NOR gate on the bottom branch, whose outputs go into a final NAND gate producing output Y.

For the circuit shown above, the equivalent gate is:

A
AND gate
B
OR gate
C
NAND gate
D
NOT gate

Answer

Correct answer:D

Step-by-step solution

Standard Method

Given: A logic circuit with inputs $A$ and $B$ .

Find: The equivalent gate of the complete circuit.

From the circuit, the top gate is a NAND gate taking inputs $A$ and $B$ . Its output is

\overline{A \cdot B}

The bottom gate is a NOR gate taking inputs $A$ and $B$ . Its output is

\overline{A + B}

These two outputs are applied to the final NAND gate. Therefore,

Y = \overline{\left(\overline{A \cdot B}\right) \cdot \left(\overline{A + B}\right)}

Now use De Morgan's law:

\overline{A \cdot B} = \overline{A} + \overline{B}

and

\overline{A + B} = \overline{A} \cdot \overline{B}

Substituting,

Y = \overline{\left(\overline{A} + \overline{B}\right) \cdot \left(\overline{A} \cdot \overline{B}\right)}

Using absorption,

\left(\overline{A} + \overline{B}\right) \cdot \left(\overline{A} \cdot \overline{B}\right) = \overline{A} \cdot \overline{B}

Hence,

Y = \overline{\overline{A} \cdot \overline{B}}

Again by De Morgan's law,

Y = A + B

Therefore, the given circuit is equivalent to an OR gate. The solution contains contradictory text, but its final declared answer is inconsistent with the actual circuit diagram. The correct equivalent gate from the circuit is OR gate, so the most defensible option is B.

Common mistakes

Mistake: Treating the lower gate as an OR gate followed by a NOT gate separately from the drawn symbol. Why wrong: the symbol shown is already a NOR gate. What to do instead: identify each gate directly from its symbol before writing Boolean expressions.
Mistake: Using the text of the solution without checking it against the circuit diagram. Why wrong: the written explanation contradicts the actual connections and gate symbols. What to do instead: derive the Boolean expression from the diagram itself and then simplify.
Mistake: Forgetting that the final gate is a NAND gate, not an AND gate. Why wrong: missing the output bubble changes the final complement and gives a wrong equivalent expression. What to do instead: always account for inversion bubbles at gate outputs.

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Answer

Step-by-step solution

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