MCQEasyJEE 2025Logic Gates

JEE Physics 2025 Question with Solution

The output of the circuit is low (zero) for:

Logic circuit with two inputs X and Y entering an OR-shaped gate, followed by a second gate with output bubble, giving final output on the right.

(A) X=0,Y=0X = 0, Y = 0

(B) X=0,Y=1X = 0, Y = 1

(C) X=1,Y=0X = 1, Y = 0

(D) X=1,Y=1X = 1, Y = 1

Choose the correct answer from the options given below:

  • A

    (A), (B) and (C) only

  • B

    (B), (C) and (D) only

  • C

    (A), (C) and (D) only

  • D

    (A), (B) and (D) only

Answer

Correct answer:A

Step-by-step solution

Standard Method

Given: A logic circuit with inputs XX and YY is shown.

Find: For which input combinations the output is low, i.e. 00.

From the solution, the circuit behaves as a NAND gate followed by a NOT gate. Therefore, the final output is the inversion of the NAND output.

Check each case:

  • For X=0,Y=0X = 0, Y = 0:
NAND(0,0)=1\text{NAND}(0,0) = 1 NOT(1)=0\text{NOT}(1) = 0

So the output is low.

  • For X=0,Y=1X = 0, Y = 1:
NAND(0,1)=1\text{NAND}(0,1) = 1 NOT(1)=0\text{NOT}(1) = 0

So the output is low.

  • For X=1,Y=0X = 1, Y = 0:
NAND(1,0)=1\text{NAND}(1,0) = 1 NOT(1)=0\text{NOT}(1) = 0

So the output is low.

  • For X=1,Y=1X = 1, Y = 1:
NAND(1,1)=0\text{NAND}(1,1) = 0 NOT(0)=1\text{NOT}(0) = 1

So the output is high.

Therefore, the output is low for (A), (B) and (C) only. The correct option is A.

Truth Table Check

Given: Input pairs are labeled as (A), (B), (C) and (D).

Find: Which labels produce final output 00.

Using the gate behavior stated in the solution:

(A):X=0,Y=0output=0(B):X=0,Y=1output=0(C):X=1,Y=0output=0(D):X=1,Y=1output=1\begin{aligned} (A) &: X=0, Y=0 \Rightarrow \text{output}=0 \\ (B) &: X=0, Y=1 \Rightarrow \text{output}=0 \\ (C) &: X=1, Y=0 \Rightarrow \text{output}=0 \\ (D) &: X=1, Y=1 \Rightarrow \text{output}=1 \end{aligned}

Hence, the low output occurs for (A), (B) and (C) only. So the correct option is A.

The solution contains inconsistent wording in one approach about gate names, but both approaches conclude the same valid set of inputs and the same correct option.

Common mistakes

  • Identifying the wrong gate from the diagram. This leads to an incorrect truth table. First confirm whether the final stage inverts the signal, then evaluate the output combinations.

  • Checking only the first gate and ignoring the effect of the second gate. The final output depends on the complete circuit, not on an intermediate gate output alone.

  • Assuming that low output occurs only when both inputs are 00. For logic circuits, every input combination must be tested systematically using the truth table.

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